NDLI: Thermal fatigue of solder flip-chip assemblies

Content Provider	IEEE Xplore Digital Library
Author	Roesner, B. Baraton, X. Guttmann, K. Samin, C.
Copyright Year	1998
Description	Author affiliation: Thomson Multimedia, Villingen, Germany (Roesner, B.)
Abstract	Recently several low cost alternatives to the flip-chip interconnection technology have been investigated. The scope of the paper is a reliability study of flip-chip assemblies on various substrates (mainly FR4). The deterioration (characterised by the electrical resistance) of 63Sn37Pb and of 96.5Sn3.5Ag bumps caused by both thermal cycling and thermal shock will be described. Samples with and without encapsulated flip-chip interconnections have been investigated. It has been found that the relationship, the number of the thermal cycles to destruction of the bumps as a function of chip size, and bump height obeys the Coffin-Manson equation. TV tuner circuits are a potential application of flip-chip technology. It has been experimentally verified that flip-chip contacts exhibit superior high frequency performance compared to those assembled in chip and wire and/or in using SO package.
Starting Page	872
Ending Page	877
File Size	926662
Page Count	6
File Format	PDF
ISBN	0780345266
ISSN	05695503
DOI	10.1109/ECTC.1998.678810
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fatigue Assembly Integrated circuit interconnections Thermal resistance Costs Electric resistance Electric shock Equations TV Tuners
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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