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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jae-Woong Nah Buchwalter, S.L. Gruber, P.A. Shih, D.Y. Furman, B.K. |
| Copyright Year | 2008 |
| Description | Author affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY (Jae-Woong Nah; Buchwalter, S.L.; Gruber, P.A.; Shih, D.Y.; Furman, B.K.) |
| Abstract | We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has shown the capability to combine low cost attributes with high performance capabilities. C4NP allows a larger number of interconnections with finer pitch than screen printing methods because it eliminates the volume reduction problem of solder paste. Also, C4NP allows more freedom in selecting the composition of solder bumps when compared with the electroplating method. To make Cu-cored flip chip interconnections with C4NP, Cu spheres are arrayed in the cavities on a mold which matches the CTE of the wafer. The Cu spheres are then transferred from the Si mold to C4NP solder bumps on the wafer by using the same process used for C4NP solder transfer. Then, after dicing, the diced chip is flip chip assembled on the substrate which has been pre-soldered. This combination of C4NP and Cu spheres is a dry process with potential for low cost, because it does not need thick photoresist, lithography, or plating process steps. Our early laboratory demonstrations of Cu-cored bumping have processed individual chips rather than full wafers; but, based on our manufacturing experience with C4NP solder bumping, we expect the process to be readily extendible to wafer scale. The C4NP Cu-cored flip chip joints offer potential advantages in stress mitigation and electrical performance. The centered Cu sphere in the joint ensures greater stand-off for fine pitch, which facilitates the underfill process and improves fatigue resistance due to the taller bump. The low electrical resistivity of Cu enhances current carrying capacity. The small Sn/Cu ratio in the bump would decrease UBM consumption and solder depletion under high current stressing. The high thermal conductivity of Cu also enhances heat transfer from the chip to the substrate. Due to the high Cu/Sn ratio in the flip chip interconnections, the higher Young's modulus of Cu over solder could be a concern for stress concentration on the IC despite the higher stand-off height provided by the Cu-core bump. However, in the C4NP Cu-cored flip chip structure, since the transfer mold is used for inserting Cu spheres into the flip chip joints, Cu spheres can be selectively deployed only to the joints where the composite bumps are required, whereas the other, highly stressed joints can be electrically connected without Cu spheres. Therefore, the selective use of composite interconnects may allow stress to be minimized while optimizing electrical performance. |
| Starting Page | 1351 |
| Ending Page | 1356 |
| File Size | 942843 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424422302 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2008.4550151 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Flip chip Costs Stress Electric resistance Tin Thermal conductivity Printing Assembly Resists Lithography |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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