NDLI: JACS-Pak/sup TM/ flip-chip chip scale package development and characterization

Content Provider	IEEE Xplore Digital Library
Author	Lindsey, S.E. Aday, J. Blood, B. Yifan Guo Hemann, B. Kellar, J. Koehler, C. Liu, J. Sarihan, V. Tessier, T. Thompson, L. Yeung, B.
Copyright Year	1998
Description	Author affiliation: Adv. Interconnect Syst. Labs., Motorola Inc., Tempe, AZ, USA (Lindsey, S.E.)
Abstract	As the drive towards smaller portable communication products continues, conventional, peripheral leaded surface mount packaging technologies are beginning to reach their practical limits. Ongoing technology development and deployment activities in the area of direct chip attach and fine pitch ball grid array packaging have been underway within Motorola for the last decade. More recently, these two core competencies have been effectively leveraged leading to the development of a robust flip chip based Chip Scale Packaging technology dubbed JACS-Pak/sup TM/ CSP. The mix of technological capabilities that enabled this rapid development and qualification are discussed in this paper. To achieve the rapid deployment goal this program has used simulations extensively from the very onset of the program. A detailed cost modeling simulation identified the three major cost contributors to the overall package costs as wafer bumping costs, interposer substrate cost and manufacturing throughput. This focused the development effort on a low cost solution. Nonlinear finite element modeling and simulation was used at every stage of package development for design evaluation, design directions and design space determination. Finite element predictions at component level and board level were validated using micro moire laser interferometry for in-plane deformation measurement and Twyman-Green interferometry for out of plane deformation measurements. A detailed reliability testing program enabled confidence in the package performance and provided validation of the finite element based life time prediction capability.
Starting Page	511
Ending Page	517
File Size	1027872
Page Count	7
File Format	PDF
ISBN	0780345266
ISSN	05695503
DOI	10.1109/ECTC.1998.678741
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Finite element methods Chip scale packaging Semiconductor device modeling Interferometry Surface-mount technology Electronics packaging Robustness Flip chip Qualifications
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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