NDLI: Correlation of flip chip underfill process parameters and material properties with in-process stress generation

Content Provider	IEEE Xplore Digital Library
Author	Palaniappan, P. Selman, P.J. Baldwin, D. Wong, C.P.
Copyright Year	1998
Description	Author affiliation: George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Palaniappan, P.)
Abstract	Package design is headed towards fewer levels of packaging and one such design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). The interconnection technique utilizes chips having solder bumps on each bond pad. The bumped chips are aligned to the substrate traces and attached using eutectic solder. As the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between these materials. To overcome this problem, a rigid encapsulant is introduced between the chip and the substrate which reduces the actual CTE mismatch thus reducing the effective stresses experienced by the solder interconnects and significantly improving long term reliability. The underfill material however, does introduce a high level of mechanical stress in the silicon die. The induced stress in the assembly is a function of the underfill material utilized, the assembly process used and the curing parameters. Therefore, the selection of underfill material is critical to achieving the desired performance and reliability. The effect of encapsulation material on the mechanical stress induced in a flip chip assembly during underfill cure was presented in previous papers (Palaniappan and Baldwin, 1997). This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing. The goal of this work is to determine the fundamental effects of assembly process history on stresses generated in low cost flip chip assemblies ultimately linking these to reliability performance. The objectives are to characterize the material properties of underfills processed under varying assembly conditions, perform in-situ stress measurements in the flip chip assemblies processed under the same conditions to characterize the stress distribution and maximum stress at the chip/underfill interface and to correlate material properties with the residual stresses as a function of assembly process parameters. In this work, the ATC04 assembly test chip from Sandia National Laboratories was used to analyze commercial underfill processed under different cure parameters. Underfill samples were cured in situ during test vehicle assembly process to determine the glass transition temperature, T/sub g/, storage modulus, G' and the coefficient of thermal expansion, CTE. Correlation between the underfill material properties, the relative stresses produced during cure, and the cure parameters are made.
Starting Page	838
Ending Page	847
File Size	1559666
Page Count	10
File Format	PDF
ISBN	0780345266
ISSN	05695503
DOI	10.1109/ECTC.1998.678805
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Assembly Packaging Material properties Residual stresses Thermal expansion Thermal stresses Testing Wiring Bonding
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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