NDLI: Super stretched solder interconnects for wafer level packaging

Content Provider	IEEE Xplore Digital Library
Author	Rajoo, R. Wong, E.H. Lim, S.S. Hnin, W.Y. Seah, S.K.W. Tay, A.A.O. Iyer, M. Tummala, R.R.
Copyright Year	2006
Description	Author affiliation: Inst. of Microelectron., Singapore (Rajoo, R.; Wong, E.H.; Lim, S.S.; Hnin, W.Y.; Seah, S.K.W.)
Abstract	A cost-effective wafer level packaging technique termed "stretch and break", based on stretching and detachment of solder interconnections, has been established. Excellent co-planarity, essential for wafer level test and burn-in, is inherent in the process. The technique allows the freedom to use solder materials of up to 400degC melting temperature for forming the interconnection. The shape of the interconnection can also be easily manipulated for optimum performance. The mechanical and thermal cycling reliabilities of the stretched solder interconnection have been found to be significantly better than those of conventional solder joints
File Size	1440222
File Format	PDF
ISBN	1424401526
ISSN	05695503
DOI	10.1109/ECTC.2006.1645809
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Integrated circuit interconnections Shape Soldering Packaging Costs Circuit testing Copper Thermal stresses Flip chip
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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