NDLI: Development of ball bump forming technology using solder paste and new simplified CSP

Content Provider	IEEE Xplore Digital Library
Author	Fujino, J. Takaki, S. Hayashi, K. Izuta, G. Hirota, J.
Copyright Year	1998
Description	Author affiliation: Manuf. Eng. Center, Mitsubishi Electr. Corp., Hyogo, Japan (Fujino, J.)
Abstract	We have investigated a new bump forming process and developed a machine using solder paste. The ball bumps formed by the machine satisfied the planned EIAJ standards. The process is as follows. First, cavities are formed by superimposing a stencil onto a base plate. Secondly, they are filled with solder paste using a screening operation and a printed circuit board (PCB) is aligned face down on the stencil. Finally, they are heated together and solder paste is reflowed to be transferred onto the pads. The separable transfer jig is suitable for mass-production compared with block-type one, reducing the flux residue cleaning time, and realizing bump forming with a 0.3 mm pitch. The bump forming machine will be applied to the mass-production of chip scale packages (CSP) with a 0.8 mm pitch at the rate of 100,000 packages a month. We have also developed a new CSP with a unique structure as an application of the bump forming process.
Starting Page	442
Ending Page	447
File Size	916971
Page Count	6
File Format	PDF
ISBN	0780345266
ISSN	05695503
DOI	10.1109/ECTC.1998.678731
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Large scale integration Packaging machines Electronics packaging Surface-mount technology Electrodes Shape control Manufacturing processes Facsimile Printed circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

CSP solder ball reliability

High-speed SMT compatible dispenseless underfill process for CSP BGA flip chip assembly

Industrial flip-chip process for CSP-3D from design to manufacturing

Double-bump surface-mount technology for very high IO interconnections

flexPAC-development and qualification of a low cost CSP

Improvements of solder ball shear strength of a wafer-level CSP using a novel Cu stud technology

E-TQHS: an enhanced performance tape carrier package

High reliability assembly of chip scale packages

CSP present and future

Development of ball bump forming technology using solder paste and new simplified CSP

Similar Documents

CSP solder ball reliability

High-speed SMT compatible dispenseless underfill process for CSP BGA flip chip assembly

Industrial flip-chip process for CSP-3D from design to manufacturing

Double-bump surface-mount technology for very high IO interconnections

flexPAC-development and qualification of a low cost CSP

Improvements of solder ball shear strength of a wafer-level CSP using a novel Cu stud technology

E-TQHS: an enhanced performance tape carrier package

High reliability assembly of chip scale packages

CSP present and future

Development of ball bump forming technology using solder paste and new simplified CSP