NDLI: Reliability of flip chip on board. First order model for the effect on contact integrity of moisture penetration in the underfill

Content Provider	IEEE Xplore Digital Library
Author	Caers, J.F.J.M. Oesterholt, R. Bressers, R.J.L. Mouthaan, T.J. Verweij, J.F.
Copyright Year	1998
Description	Author affiliation: Philips Centre for Manuf. Technol., Eindhoven, Netherlands (Caers, J.F.J.M.)
Abstract	In evaluating the reliability of flip chip on board with solder bumps, only a little is known about moisture-induced failure mechanisms at interconnection level. In order to accommodate the difference in coefficient of thermal expansion of the silicon die and the printed board in a flip chip geometry, an epoxy underfill is commonly applied. This underfill increases the resistance to cyclic temperature loads, but the material is susceptible to moisture ingress. Failure analysis of flip chips from an 85/spl deg/C/85%RH test has shown that swelling of the underfill caused by moisture take up and the resulting hygro-stress is a major driving force for failures at interconnection level. To capture this failure mechanism, a new first order, one dimensional diffusion model for moisture is used. Moisture absorption properties of underfills are experimentally determined by gravimetric vapour sorption experiments at 85/spl deg/C/85%RH. The temperature dependencies of these properties are estimated based on data of similar epoxy moulding compounds. Taking a critical hygro-stress level as failure criterion, an analytical transform is proposed, and an acceleration factor defined. A design rule for accelerated humidity testing is formulated. The acceleration transform is used to plot iso failure-free time diagrams for two flip chip underfills. These diagrams enable predicting of a failure-free time during service life under a variety of temperature and humidity conditions.
Starting Page	867
Ending Page	871
File Size	494388
Page Count	5
File Format	PDF
ISBN	0780345266
ISSN	05695503
DOI	10.1109/ECTC.1998.678809
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Failure analysis Moisture Temperature Testing Acceleration Humidity Thermal expansion Silicon Geometry
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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Evaluation of alternative materials for system-on-package (SOP) substrates

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