NDLI: Optimization of Microelectrode Design for Cortical Recording Based on Thermal Noise Considerations

Content Provider	IEEE Xplore Digital Library
Author	Lempka, S.F. Johnson, M.D. Barnett, D.W. Moffitt, M.A. Otto, K.J. Kipke, D.R. McIntyre, C.C.
Copyright Year	2006
Description	Author affiliation: Dept. of Biomed. Eng., Cleveland Clinic Found., OH (Lempka, S.F.)
Abstract	Intracortical microelectrode recordings of neural activity show great promise as control signals for neuroprosthetic applications. However, faithful, consistent recording of single unit spiking activity with chronically implanted silicon-substrate microelectrode arrays has proven difficult. Many approaches seek to enhance the long-term performance of microelectrode arrays by, for example, increasing electrode biocompatibility, decreasing electrode impedance, or improving electrode interface properties through application of small voltage pulses. The purpose of this study was to use computational models to optimize the design of microelectrodes. We coupled detailed models of the neural source signal, silicon-substrate microelectrodes, and thermal noise to define the electrode contact size that maximized the signal-to-noise ratio (SNR). Model analysis combined a multi-compartment cable model of a layer V cortical pyramidal neuron with a 3D finite element model of the head and microelectrode to define the amplitude and time course of the recorded signal. A spatially-lumped impedance model was parameterized with in vitro and in vivo spectroscopy data and used to define thermal noise as a function of electrode contact size. Our results suggest that intracortical microelectrodes with a contact size of ~380 $mum_{2}$ will provide an increased SNR in vivo and improve the long-term recording capabilities of silicon-substrate microelectrode arrays
Sponsorship	IEEE EMB
Starting Page	3361
Ending Page	3364
File Size	383133
Page Count	4
File Format	PDF
ISBN	1424400325
ISSN	1557170X
DOI	10.1109/IEMBS.2006.259432
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Microelectrodes Electrodes Signal to noise ratio Impedance In vivo Neural prosthesis Voltage Computational modeling Signal analysis
Content Type	Text
Resource Type	Article
Subject	Signal Processing Biomedical Engineering Health Informatics Computer Vision and Pattern Recognition

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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