NDLI: Effects of lead bonding process on reliability of chip scale package

Content Provider	IEEE Xplore Digital Library
Author	Lee, Y.J. Eyre, M.W.
Copyright Year	2000
Description	Author affiliation: Electron. Packaging Mater. Dev., Dow Corning Corp., Midland, MI, USA (Lee, Y.J.)
Abstract	An integrated circuit (IC) package has become smaller and its profile becomes lower as new chip scale packaging (CSP) designs have been introduced. A new design of packages demands new materials and optimization of manufacturing processes to enhance reliability of the package. A compliant layer in Tessera's /spl mu/-BGA(R) package is a crucial component to increase solder ball reliability in the board level assembly. The compliant layer can reduce damage to the solder balls, which is induced by mismatch of the coefficient of thermal expansion (CTE) between Si die and the printed circuit board (PCB). Silicone elastomer is one of the best candidate for the compliant layer due to its low modulus and low moisture absorption. While the colder ball reliability in the /spl mu/-BGA package is significantly improved due to its unique design and optimal materials set, fatigue damage can be imposed on beam leads inside of the package during thermal cycling. To reduce the damage in the package, an optimal lead (or beam lead) bonding process becomes critical for flex circuit interposer type of CSP designs including /spl mu/-BGA. Three dimensional (3D) Finite Element Analysis (FEA) of the lead bonding and subsequent thermal cycling, is conducted to show effects of designs of the lead (dimensions and shapes) as well as the lead bonding process parameters. Several different loci of a bond tool motion are numerically simulated to determine optimal lead bonding parameters based on the calculated damage accumulated in the deformed shape of leads during the lead bonding process followed by the thermal cyclings.
Starting Page	1392
Ending Page	1397
File Size	602472
Page Count	6
File Format	PDF
ISBN	0780359089
DOI	10.1109/ECTC.2000.853391
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bonding processes Lead Chip scale packaging Integrated circuit packaging Integrated circuit reliability Materials reliability Shape Design optimization Manufacturing processes Assembly
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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