NDLI: Meeting the heat removal requirements of 'tiled' compliant wafer level packages

Content Provider	IEEE Xplore Digital Library
Author	Patel, C.S. Agraharam, S. Martin, K. Meindll, J.D.
Copyright Year	2000
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Patel, C.S.)
Abstract	The 'tiling' of wafer level packages yields the maximum increase in the performance and the packing efficiency. The limitations on the 'tiling' are posed by the capability of removing the heat from all the applications ranging from low power to high power. This paper presents a thorough analysis of the optimum thermal design of the wafer level package and the system assembly to meet the high performance heat removal requirements while maintaining the 'tiled' assembly. The results indicate that even with heat sink fin aspect ratio of 100:1, it is not possible to remove the heat from the 'tiled' high performance wafer level package assembly. An optimum methodology is developed to determine the placement of components on the beard such that the heat can be removed without sacrificing the 'tiled' assembly. By using this methodology, the fin aspect ratio of 25 and 50 is sufficient to meet the cost performance and high performance applications' heat removal requirements, respectively.
Starting Page	278
Ending Page	286
File Size	708960
Page Count	9
File Format	PDF
ISBN	0780359089
DOI	10.1109/ECTC.2000.853164
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Assembly systems Electronic packaging thermal management Heat sinks Integrated circuit packaging Thermal management Chemical technology Costs Power dissipation Integrated circuit modeling
Content Type	Text
Resource Type	Article

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