NDLI: Bridging the gap: package level and system level thermal modeling

Content Provider	IEEE Xplore Digital Library
Author	Wang, W. Liou, S. Sun, Y.S. Lai, J.Y. Tien, C. Her, T.D. Michael, M.
Copyright Year	2000
Description	Author affiliation: Siliconware USA Inc., San Jose, CA, USA (Wang, W.)
Abstract	The thermal performance is one of the critical issues in electronic packaging. The thermal data provided by the packaging suppliers are normally on the package level. This is very informative for comparing different packages. The system customers, on the other hand, are more concerned about the package thermal performance in their specific systems. This paper has investigated the methodology of correlating the data of these two different levels. The CFD tool Flotherm has been used for both package level and system level modeling. For package level modeling, the results are compared with the standard JEDEC testing data. For system level modeling, a critical ASIC chip is packaged in a standard BGA package mounted on a custom board. There are other chips on the board such as memories and a power device. The custom board is installed in a PC system. The various components are modeled at different levels of detail, including full detail model, lumped model, and simple compact model. The focus here is to determine the junction temperature of the critical ASIC component in the complex system. The modeling is optimized for this purpose to reduce computation cost. The two levels of modeling have very different length scales, which makes the correlation between them challenging job. This paper investigated the possibility and sensitivity of such simulation. It is demonstrated that properly conducted computer modeling can be a powerful tool for both package thermal characterization and system thermal design.
Starting Page	287
Ending Page	293
File Size	598787
Page Count	7
File Format	PDF
ISBN	0780359089
DOI	10.1109/ECTC.2000.853165
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronic packaging thermal management Power system modeling Application specific integrated circuits Thermal conductivity Electronics packaging Computational fluid dynamics Testing Temperature sensors Cost function Computational efficiency
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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