NDLI: Manufacturing productivity improvements for PBGA and flip chip substrates in PWB factory

Content Provider	IEEE Xplore Digital Library
Author	Chrzanowski, D.E. Stanke, D.A. Lapcevich, R.A.
Copyright Year	2000
Description	Author affiliation: IBM Interconnect Products, Endicott, NY, USA (Chrzanowski, D.E.)
Abstract	This paper discusses the new techniques applied to a conventional PWB manufacturing line to improve productivity and maximize capacity for PBGA and flip chip substrate products. We discuss equipment modifications and processing productivity improvements in the areas of test, handling, panel layout and singulation. The challenge has been to create process steps to match specific and sometimes unique requirements, which often resulted in sub optimization of the product through the factory standard 19.5"/spl times/24" panel. Traditional PWB card dimensions range from one up on a standard panel size to cards as small as 3"/spl times/5" repeated within the panel framework. These panels are typically profiled to final shipped format and do not have symmetrical dimensions. With the industry trends for PBGA and flip chip substrates evolving to higher I/O, less space, chip scale packaging, and large volumes, productivity has a direct correlation to panel utilization. PBGA sizes, typically square or rectangular, allow for improved optimization through the use of processes that are typically seen in wafer and ceramic substrate manufacturing. The singulation and testing equipment required a high degree of cross industry thinking to integrate it within the conventional PWB equipment set. We describe specific changes to the factory, which includes modified equipment for singulation and processing. We also describe the advantages and challenges that each of the improvements has to overall throughput and cost efficiency in the PWB line. Finally we demonstrate how we executed significant improvements to the quality and consistency of the final product.
Starting Page	558
Ending Page	562
File Size	381384
Page Count	5
File Format	PDF
ISBN	0780359089
DOI	10.1109/ECTC.2000.853213
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Productivity Flip chip Testing Production facilities Pulp manufacturing Aerospace industry Chip scale packaging Ceramics Manufacturing processes Manufacturing industries
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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