NDLI: One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications

Content Provider	IEEE Xplore Digital Library
Author	Mirza, A.R.
Copyright Year	2000
Description	Author affiliation: Electron. Visions Inc., Phoenix, AZ, USA (Mirza, A.R.)
Abstract	The ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate is becoming a critical issue for a variety of semiconductor applications. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3-D interconnect processes. In the microelectromechanical systems (MEMS) arena, accurate alignment of two silicon micromachined wafers enables the design of more advanced MEMS devices and aggressive die shrinks of existing products. In this paper we discuss the advantages and disadvantages of various substrate-to-substrate alignment techniques including infrared, through wafer via, inter-substrate optical and wafer backside alignment methods. We also report on a new approach to wafer-to-wafer alignment that relies on precision alignment positioning systems to register and align wafers with one micron or better precision. Test results from this wafer-to-wafer alignment system demonstrate that one micron alignment accuracy can be routinely obtained. This new wafer-level alignment and bonding technique is particularly well suited for high-volume manufacturing due to the long-term stability of the precision alignment positioning system. This paper gives a brief overview of some typical uses of aligned wafer-level bonding for chip-scale, 3-D interconnect and MEMS applications.
Starting Page	676
Ending Page	680
File Size	517874
Page Count	5
File Format	PDF
ISBN	0780359089
DOI	10.1109/ECTC.2000.853231
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer bonding Silicon CMOS technology Micromechanical devices Substrates CMOS process Chip scale packaging Semiconductor device packaging Wafer scale integration Microelectromechanical systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Thru-Wafer Interconnect for SOI-MEMS 3D Wafer-Level Hermetic Packaging

Wafer-level packaging technology for MEMS

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

MEMS Oscillators for High Volume Commercial Applications

Fabrication and characterization of a novel wafer-level chip scale package for MEMS devices

MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integration

Low temperature bonding process for wafer-level MEMS packaging

MEMS vacuum packaging technology and applications

Wafer Scale Encapsulation of MEMS Devices

One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications

Similar Documents

Thru-Wafer Interconnect for SOI-MEMS 3D Wafer-Level Hermetic Packaging

Wafer-level packaging technology for MEMS

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

MEMS Oscillators for High Volume Commercial Applications

Fabrication and characterization of a novel wafer-level chip scale package for MEMS devices

MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integration

Low temperature bonding process for wafer-level MEMS packaging

MEMS vacuum packaging technology and applications

Wafer Scale Encapsulation of MEMS Devices

One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications