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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Akturk, A. Potbhare, S. Goldsman, N. Lelis, A. |
| Copyright Year | 2009 |
| Description | Author affiliation: Army Research Laboratory, Adelphi, MD, USA (Lelis, A.) || Department of Electrical and Computer Engineering, University of Maryland College Park, USA (Akturk, A.; Potbhare, S.; Goldsman, N.) |
| Abstract | We investigate the chip heating in silicon carbide (SiC) double diffused power MOSFETs at the resolution of DMOSFET cells (typically > 30,000 cells per power chip [1]). To achieve this, we develop unique chip and device simulators for determining the coupled electrical and thermal performance. Specifically, we first start by obtaining the electrical operational details of a typical power chip cell by solving for the coupled semiconductor equations and the Poisson equation. We also resolve the feedback between the electrical and thermal dynamics within this cell by self-consistently coupling the differential heat flow equation to the electrical performance equations. The cell level, described so far, provides the voltage and temperature dependent electrical characteristics as well as the heat generated for a typical power chip cell. We then proceed to the power chip level by first finding the locations of these individual cells. These locations along with the layout details such as fabrication materials (metals, substrate, insulators and package materials) and their dimensions between individual devices or between the devices at the edge and the outside help us calculate the associated thermal resistances between our thermal nodes, which correspond to individual cells. The electrical simulation of the cell is used to calculate space and temperature dependent local heat generated on the chip. These local heat generated figures are then fed to the power integrated circuit (IC) thermal network to solve for a temperature profile. We iterate between the temperature profile calculated at the power chip level and the heat generated at the cell level due to electrical flow until all local cell temperatures and heat generated calculated using the thermal network and the electrical cell simulator, respectively, agree at both levels. The feedback between the IC thermal and device electrical network is conceptually shown in Fig. 1. The heat generated at the resolution of a single cell and the temperature calculated by coupling that cell to the rest of the chip are iterated until a self-consistent heat generated and temperature map for the entire chip is achieved. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 767394 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424460304 |
| DOI | 10.1109/ISDRS.2009.5378139 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon carbide Cooling |
| Content Type | Text |
| Resource Type | Article |
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