NDLI: Simulation study for suppressing corner effect in a saddle MOSFET for Sub-50 nm high density high performance DRAM cell transistor

Content Provider	IEEE Xplore Digital Library
Author	Pervez, S.A. Heesang Kim Byung-Gook Park Hyungcheol Shin
Copyright Year	2009
Description	Author affiliation: School of Electrical Engineering, Seoul National University Seoul 151-742, Republic of Korea (Pervez, S.A.; Heesang Kim; Byung-Gook Park; Hyungcheol Shin)
Abstract	Saddle MOSFET (S-MOSFET), a device with a recess channel having tri-gate controllability over the channel, shows improved characteristics in controlling short channel effects and higher drive current compared with conventional recessed channel devices [1]. On the other hand, tri-gated structure has some disadvantages caused by corner effect, which can result in unstable threshold voltage (V) characteristics by early turn-on. This premature corner inversion leads to several problems like lower V, larger leakage current and the I ratio degradation, consequently [2,3]. In this work, we have examined the reasons for the abnormal corner effect, its impact on the device characteristics, and possible approaches to suppress it. The corner effect in S-MOSFET resembles that of bulk FINFET [4] and thus should be dealt accordingly. Simulations have been performed on Sentaurus, a drift-diffusion based 3-D device simulator [5]. Device is designed using Sentaurus Process Emulator. Hurkx [6] band-to-band tunneling model is combined with Shockley-Read-Hall recombination to simulate realistic values of OFF-state leakage current.
Starting Page	1
Ending Page	2
File Size	203106
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378226
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Random access memory Leakage current Electrons Doping Educational institutions Controllability Threshold voltage Degradation FinFETs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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