NDLI: Silicon nanowire nonvolatile-memory with varying HfO charge trapping layer thickness

Content Provider	IEEE Xplore Digital Library
Author	Zhu, X. Qiliang Li Ioannou, D.E. Gu, D. Baumgart, H. Bonevich, J.E. Suehle, J.S. Richter, C.A.
Copyright Year	2009
Description	Author affiliation: Dept. of Electrical Engineering, Old Dominion University, Norfolk, VA 23529 (Gu, D.; Baumgart, H.) \|\| National Institute of Standards and Technology, Gaithersburg, MD 20899 (Bonevich, J.E.; Suehle, J.S.; Richter, C.A.) \|\| ECE Dept., George Mason University, Fairfax, VA 22020 (Zhu, X.; Qiliang Li; Ioannou, D.E.)
Abstract	There is a widely recognized need for urgent progress in non-volatile memory (NVM) technology, driven by the exponential market growth of ubiquitous portable and mobile electronics. To enable further scaling and achieve better portable electronics, the industry consensus is that fundamentally new innovations must be introduced beyond the 45-nm lithography node generation [1]. One of the approaches is to design NVM cells based on silicon nanowires (SiNWs) [2, 3]. The cylindrical symmetry of SiNWs leads to two aspects that enable SiNW NVM to outperform conventional planar FLASH NVM. (1) The electric field is more efficiently applied on the nanowire channel with the same control gate voltage, leading to higher performance at lower operation power. (2) Short channel lengths are possible with a minimal reduction of the dielectric stack thickness (to maintain good retention), making SiNW is particularly suitable for scaled NVM cells [4, 5]. Moreover, the use of high-k dielectric materials as gate stack and information storage medium will significantly improve the program speed and reliability for non-volatile memory [6].
Starting Page	1
Ending Page	2
File Size	219851
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378132
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Hafnium oxide Nonvolatile memory Tunneling Aluminum oxide Degradation Electron traps Consumer electronics Lithography Nanowires
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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