NDLI: Scaling of the SOI field effect diode (FED) for memory application

Content Provider	IEEE Xplore Digital Library
Author	Yang Yang Gangopadhyay, A. Qiliang Li Ioannou, D.E.
Copyright Year	2009
Description	Author affiliation: Department of Electrical and Computer Engineering, George Mason University, VA 22020, USA (Yang Yang; Gangopadhyay, A.; Qiliang Li; Ioannou, D.E.)
Abstract	Memory arrays consume a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory cell (6T-SRAM) and the (one transistor/one capacitor) dynamic memory (DRAM) both suffer from excessive leakage current. Consequently, there is a widely recognized need for urgent progress in memory technology. The Thin Capacitively Coupled Thyristor (TCCT) based memory cell (T-RAMs) approach is a most promising, CMOS compatible alternative to the “standard” cell both for SRAM [1] and DRAM cell [2] designs. However, the T-RAMs demand the precise control of doping profiles of the pn junctions so as to achieve correct breakdown characteristics. To address these difficulties, we explored the possibility of replacing the thyristor with a suitable Field Effect Diode (FED), which displays similar I–V characteristics without suffering from the above technological drawbacks [3]. In this paper, we studied the scalability of the FED and compare it with TCCT by numerical simulations.
Starting Page	1
Ending Page	2
File Size	306006
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378045
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Diodes Random access memory Thyristors Chip scale packaging SRAM chips Capacitors Leakage current CMOS technology Doping profiles P-n junctions
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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