NDLI: Influence of polysilicon thickness on the microwave attenuation losses of the CPWs fabricated on polysilicon-passivated high-resistivity silicon substrates

Content Provider	IEEE Xplore Digital Library
Author	Chao-Jung Chen Ruey-Lue Wang Yan-Kuin Su Chun-Yuan Huang Yung-Feng Chen Cheng-Yuan Hung
Copyright Year	2009
Description	Author affiliation: Department of Applied Science, National Taitung University, Taitung, Taiwan (Chun-Yuan Huang) \|\| Department of Electrical Engineering, National Kaohsiung Normal University, Kaohsiung, Taiwan (Ruey-Lue Wang) \|\| Advanced Optoelectronic Technology Center, Institute of Microelectronics, and Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan (Chao-Jung Chen; Yan-Kuin Su; Yung-Feng Chen) \|\| Department of Electronics Engineering and Computer Science, Tung-Fang Institute of Technology, Taiwan (Cheng-Yuan Hung)
Abstract	In recent years, a high resistivity silicon (HR-Si) substrate is of interest as a substrate upon which integrated radio-frequency (RF) and millimeter wave circuits can be realized. Because the material have an inherent defect density, surface effect and resistivity degradation near the interface between an insulating oxide and a HR-Si substrate tend to overshadow the potentially low RF loss levels in HR-Si substrate. Fixed positive charges within the oxide attract free carriers near the substrate surface, leading to an accumulation or inversion layer on the silicon surface. Consequently, these free carriers act as the thin surface-channel at the Si/oxide interface, thus reducing the resistivity of the silicon surface and increasing the substrate loss. In fact, several surface passivation approaches have been used to overcome these shortcomings. For example, local resistivity can be enhanced by high-dose implantation (e.g, argon) to convert LR-Si substrate to HR-Si substrate [1], or a trap-rich passivation layer (e.g., polysilicon or amorphous silicon) between the oxide layer and the HR-Si substrate to prevent the carrier accumulation [2]. Polysilicon films deposited by LPCVD are the most widely used as a surface passivation layer on on HR-Si substrate and a thickness between 300nm and 400 nm were generally used. For HR-Si surface passivation application, the properties of LPCVD-deposited polysilicon (or amorphous silicon) are known to be significantly dependent on deposition conditions and annealing conditions [3].
Starting Page	1
Ending Page	2
File Size	279555
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378185
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Attenuation Silicon Substrates Conductivity Grain boundaries Coplanar waveguides Semiconductor films Aluminum Testing Scattering parameters
Content Type	Text
Resource Type	Article

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