NDLI: 20GHz low power CMOS single chip receiver using resonant transformer techniques for enhanced demodulation efficiency

Content Provider	IEEE Xplore Digital Library
Author	Bo Li Bo Yang Salter, T. Yiming Zhai Goldsman, N.
Copyright Year	2009
Description	Author affiliation: Laboratory for Physical Sciences, College Park, MD 20740, USA (Salter, T.) \|\| Department of Electrical and Computer Engineering, University of Maryland, College Park, Maryland, 20742, USA (Bo Li; Bo Yang; Yiming Zhai; Goldsman, N.)
Abstract	Smart Dust Systems (SDSs) are typically very low cost wireless ad-hoc networks distributed over a relatively small area which sense, transmit and receive signals. They can be used in applications such as health monitoring, environment sensing and temporal wireless services [1]. The distributed network is composed of wireless nodes, each including antennas, transceivers and digital controllers. Minimizing both cost and power are important requirements for SDS applications. SDSs also require that each node has very small dimensions that are on the cubic millimeter scale. It is difficult to fit an antenna into such a small volume. For example, at 2 GHz, a half-wave dipole antenna is 7.5cm [2]. Using low loss dielectric material, the state of the art FICA (F-Inverted Compact Antenna) at 2.2 GHz has a size of 12mm × 12mm × 3mm [2]. This is still larger than the SDS requirement. Since the chip size is commonly a few $mm^{2},$ it is clear the antenna size dominates the system size. High frequency operation is a promising way to reduce antenna size since it is inversely proportional to the carrier frequency. For example, theoretically a FICA antenna can be scaled to millimeter range at 20 GHz. To achieve the millimeter size requirements, while also minimizing cost, in this work, we take advantage of CMOS scaling to design an inexpensive 0.13µm CMOS-based amplitude shift keying (ASK) radio frequency receiver that operates at 20 GHz. Resonant transformer circuits which increase voltage levels have also been used to improve system sensitivity [1,3].
Starting Page	1
Ending Page	2
File Size	179077
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378023
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resonance Demodulation Frequency Inductors Capacitors Voltage RLC circuits Energy consumption Circuit simulation Educational institutions
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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