NDLI: Fabrication and characterization of buried-gate fin and recess channel MOSFET for high performance and low GIDL current

Content Provider	IEEE Xplore Digital Library
Author	Jae Young Song Jong Pil Kim Sang Wan Kim Jeong-Hoon Oh Kyung-Chang Ryoo Min-Chul Sun Garam Kim Hyun Woo Kim Jisoo Chang Sunghun Jung Hyungcheol Shin Byung-Gook Park
Copyright Year	2009
Description	Author affiliation: Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul, 151-742, Korea (Jae Young Song; Jong Pil Kim; Sang Wan Kim; Jeong-Hoon Oh; Kyung-Chang Ryoo; Min-Chul Sun; Garam Kim; Hyun Woo Kim; Jisoo Chang; Sunghun Jung; Hyungcheol Shin; Byung-Gook Park)
Abstract	The fin type device has been considered as one of the most promising candidates in CMOS scaling because of excellent current drivability and good short-channel effect immunity. It is well known that the fin width should be small for proper short-channel behavior [1]. However, the narrow fin can induce a large parasitic series resistance. Therefore, it is prefered to rebuild the source/drain region. In addition, the large gate-induced drain leakage (GIDL) caused by the field concentration effect at the corner of the fin is the problem of the FinFET structure. Recently, the silicon epitaxial re-growth is used to extend the source/drain fin outside of the gate region [2]. However, there are some issues such as the cost, throughput and process complexity.
Starting Page	1
Ending Page	2
File Size	790922
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378069
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication MOSFET circuits Silicon FinFETs Threshold voltage Scanning electron microscopy Electron devices Educational institutions Sun Region 2
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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