NDLI: Modeling of perimeter-gated silicon avalanche diodes fabricated in a standard single-well CMOS process

Content Provider	IEEE Xplore Digital Library
Author	Akturk, A. Dandin, M. Goldsman, N. Abshire, P.
Copyright Year	2009
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Maryland College Park, USA (Akturk, A.; Dandin, M.; Goldsman, N.; Abshire, P.)
Abstract	We investigate design, fabrication and numerical modeling details of a silicon impact ionization device that was implemented in a standard CMOS process line for use in biomedical applications. To obtain the performance metrics of an avalanche silicon diode fabricated using a standard 0.5 µm CMOS process, and to examine possible ways to improve device characteristics using process variations and electrical control, we designed various low photon count avalanche diodes. We then laid out these diode designs with different well geometries and control terminals, had them fabricated in different process runs, and later tested them individually. To guide the design, understand the device behavior, and determine carrier impact ionization dictated performance figures, we also developed a device simulator verified by experimental data. The simulator is optimized for analysis of avalanche breakdown. Furthermore, to achieve as-designed device and circuit performance by suppressing unwanted peripheral corner breakdown between a $p^{+}-implant$ and a surrounding n-well, we used the overlapping between adjacent n-well implants. In a standard CMOS process that allows n-, $n^{+}-$ and $p^{+}-$ implants on a $p^{-}$ substrate, the n-wells were laid out by a length shorter than the process design kit recommended cross-talk distance 9λ, λ being half of the feature size. In addition to going beyond the standard process design rules to experiment with the effects of the lateral diffusion of dopants on device performance, we also added electrical gain and performance controllability to our impact ionization diodes by employing gate electrodes located at the perimeter.
Starting Page	1
Ending Page	2
File Size	88807
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378222
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Silicon Diodes CMOS process Impact ionization Process design Fabrication Numerical models Semiconductor process modeling Dark current
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design, modeling and fabrication of a CMOS compatible p-n junction avalanche photodiode

Breakdown and optical response of CMOS perimeter gated single-photon avalanche diodes

A Single-Photon Avalanche Diode in CMOS 0.5μm n-well process

A SPICE model for perimeter-gated single photon avalanche diode

Technology CAD: technology modeling, device design and simulation

Dark current in standard CMOS pinned photodiodes for Time-of-Flight sensors

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

A TCAD and Spectroscopy Study of Dark Count Mechanisms in Single-Photon Avalanche Diodes

Optimization of perimeter gated SPADs in a standard CMOS process

Modeling of perimeter-gated silicon avalanche diodes fabricated in a standard single-well CMOS process

Similar Documents

Design, modeling and fabrication of a CMOS compatible p-n junction avalanche photodiode

Breakdown and optical response of CMOS perimeter gated single-photon avalanche diodes

A Single-Photon Avalanche Diode in CMOS 0.5μm n-well process

A SPICE model for perimeter-gated single photon avalanche diode

Technology CAD: technology modeling, device design and simulation

Dark current in standard CMOS pinned photodiodes for Time-of-Flight sensors

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

A TCAD and Spectroscopy Study of Dark Count Mechanisms in Single-Photon Avalanche Diodes

Optimization of perimeter gated SPADs in a standard CMOS process

Modeling of perimeter-gated silicon avalanche diodes fabricated in a standard single-well CMOS process