NDLI: A design methodology for maximizing the voltage gain of strained Si MOSFETs using the thickness of the silicon-germanium strain relaxed buffer as a design parameter

Content Provider	IEEE Xplore Digital Library
Author	Alatise, O. Kwa, K. Olsen, S. O'Neill, A.
Copyright Year	2009
Description	Author affiliation: School of Electrical, Electronic and Computer Engineering, Newcastle University, United Kingdom., NE1 7RU (Alatise, O.; Kwa, K.; Olsen, S.; O'Neill, A.)
Abstract	Due to the low thermal conductivity of silicon-germanium (SiGe), self-heating is known to be a limiting factor of the on-state performance enhancement in deep submicrometer strained Si MOSFETs on SiGe strain relaxed buffers (SRBs). At high power densities, self-heating can cause negative drain conductance (-g), negative voltage gain (-A) and anomalous circuit operation through non-linear phase shifts [1]. It has been shown that negative self-gain from self-heating limits the design space of strained Si analog MOSFETs [1]. To reduce the impact of self heating and improve the design space of strained Si analog MOSFETs, thin SiGe SRBs have been proposed to improve heat flow efficiency by reducing the thermal resistance (R) [2]. However, in this study, it is shown that self-heating can be advantageous from the perspective of maximizing the voltage gain (A) of strained Si MOSFETs and push-pull inverting amplifiers if it is controlled properly. Using electrical measurements and calibrated TCAD electrothermal models, a design methodology for maximizing the voltage gain and avoiding negative drain conductance is presented by using the thickness of the SiGe SRB as a design parameter.
Starting Page	1
Ending Page	2
File Size	638792
Page Count	2
File Format	PDF
ISBN	9781424460304
DOI	10.1109/ISDRS.2009.5378304
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Germanium silicon alloys Silicon germanium Voltage MOSFETs Inverters Semiconductor device modeling Space heating Thickness control Design methodology Capacitive sensors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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