NDLI: Recent progress in development of SOI pixel detectors

Content Provider	IEEE Xplore Digital Library
Author	Miyoshi, T.
Copyright Year	2010
Description	Author affiliation: Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), 1-1, Oho, Tsukuba, Ibaraki 305-0801 Japan (Miyoshi, T.)
Abstract	We are developing monolithic pixel detectors with a 0.2 um CMOS, fully-depleted silicon-on-insulator (SOI) technology. The substrate is high-resistivity silicon and works as a radiation sensor having p-n junctions. The SOI layer is a 40 nm thick silicon, where readout electronics is implemented. There is a buried oxide (BOX) layer between these silicon layers. There is no mechanical bonding in the SOI pixel detector between sensor and front-end electronics, so fine segmentation and lower mass are expected compared with hybrid detectors. These kinds of pixel detectors are also useful in various research fields, such as high-energy physics, X-ray material analysis, astrophysics and medical sciences. We have already done several Multi Project Wafer (MPW) runs by gathering many pixel designs into a photo mask set. In this document, ongoing R&Ds are described. One of recent progress is the implementation of the Buried P-Well (BPW) process. The effectiveness of the BPW was evaluated by including the pixel detector design. The other steps to proceed this R&D project are also described.
Starting Page	1885
Ending Page	1888
File Size	1287927
Page Count	4
File Format	PDF
ISBN	9781424491063
ISSN	10957863
e-ISBN	9781424491056
DOI	10.1109/NSSMIC.2010.5874102
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Detectors Silicon on insulator technology Transistors Capacitance Silicon Layout
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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