NDLI: ATLAS silicon microstrip tracker operation and performance

Content Provider	IEEE Xplore Digital Library
Author	Vankov, P.
Copyright Year	2010
Description	Author affiliation: Deutsches Elektronen Synchrotron, DESY at Hamburg, Germany (Vankov, P.)
Abstract	In December 2009 the ATLAS experiment at the CERN Large Hadron Collider (LHC) recorded the first proton-proton collisions at a center-of-mass energy of 900 GeV and this was followed by the unprecedented energy of 7 TeV in March 2010. The SemiConductor Tracker (SCT) is the key precision tracking device in ATLAS, made up from silicon microstrip detectors processed in the planar p-in-n technology. The completed SCT has been installed inside the ATLAS experimental hall. After the commissioning phase it arrived to the first LHC pp collision runs in very good shape: 99.3% of the SCT modules are operational, noise occupancy and hit efficiency exceed the design specifications, the alignment is already close enough to the ideal one to allow on-line track reconstruction and invariant mass determination. This overview presents the current status of the SCT, including results from the latest data-taking periods in 2009 and 2010, and from the detector alignment. We report on the operation of the detector and observed problems. The main emphasis is given to the performance of the SCT with the LHC in collision mode in a comparison with the expected parameters and with the Monte-Carlo simulations.
Starting Page	939
Ending Page	943
File Size	3477523
Page Count	5
File Format	PDF
ISBN	9781424491063
ISSN	10957863
e-ISBN	9781424491056
DOI	10.1109/NSSMIC.2010.5873900
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large Hadron Collider Detectors Strips Silicon Physics Noise Monte Carlo methods
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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