NDLI: Correlation of flip chip underfill process parameters and material properties with in-process stress generation

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Correlation of flip chip underfill process parameters and material properties with in-process stress generation

Content Provider	IEEE Xplore Digital Library
Author	Palaniappan, P. Baldwin, D.F. Selman, P.J. Jaili Wu Wong, C.P.
Copyright Year	1999
Abstract	Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society International Microelectronics Assembly and Packaging Society (IMAPS)
Starting Page	53
Ending Page	62
Page Count	10
File Size	1301459
File Format	PDF
ISSN	1521334X
Volume Number	22
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-01-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Material properties Assembly Residual stresses Thermal stresses Electronics packaging Integrated circuit interconnections Costs Electronic packaging thermal management Thermal expansion
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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