NDLI: Industrial flip-chip process for CSP-3D from design to manufacturing

Content Provider	IEEE Xplore Digital Library
Author	Clot, P. Zeberli, J.-F. Ferrando, F. Chenuz, J.-M.
Copyright Year	2000
Description	Author affiliation: Valtronic SA, Les Charbonnieres, Switzerland (Clot, P.)
Abstract	In order to respond to need for miniaturization, Valtronic has industrialized a new flip-chip process which is well suited to organic substrates. This paper describes industrial application of this flip-chip process using gold stud bump connections with a nonconductive paste (NCP); the resulting connections are not soldered to the PWB pads, but are based on purely mechanical contact. This technique does not require any further operation such as underfilling once the die is flipped, and is suitable for organic substrates where TCE mismatches are critical concerns. In addition, it can be applied to both production runs and prototyping. Die bumping can be easily processed on either a whole wafer or a single part, and does not require any pad preparation of the pads such as under-bump metallization (UBM) before bumping. As the bumps are crushed on the PWB electrodes, they adapt their shape to the surface where the contacts are located, allowing flip-chip on flex PWB where planarity is sometimes critical. The process was applied to electronic modules for hearing aids, where extreme miniaturization is essential, and a new CSP-3D package was developed. First, dice are connected to the top face of a flat flexible substrate, then miniature SMT components are soldered on the bottom face, and the third dimension is obtained by bending and/or rolling the substrate on itself, accomplishing a 3D package. Finally, the package is filled with epoxy if required. These techniques are being used for a wide range of applications, such as CSP and MCM.
Starting Page	19
Ending Page	26
File Size	871368
Page Count	8
File Format	PDF
ISBN	0780364821
ISSN	10898190
DOI	10.1109/IEMT.2000.910704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-03
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gold Production Prototypes Metallization Electrodes Shape Hearing aids Electronics packaging Surface-mount technology Chip scale packaging
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in