NDLI: Fabrication of high-quality multilayer structure for HTS-SFQ circuits using surface treatments

Content Provider	IEEE Xplore Digital Library
Author	Nakayama, K. Ishimaru, Y. Wakana, H. Adachi, S. Tarutani, Y. Tanabe, K.
Copyright Year	2002
Abstract	Surface treatments have been applied to a multilayer structure in order to improve its surface smoothness and crystallinity for fabricating HTS-SFQ circuits. The surface treatments consist of ion beam etching and annealing in oxygen atmosphere. These surface treatments were applied to a SrSnO/sub 3/ insulating layer on a La-YBCO grandplane as an underlayer for growth of a La-YBCO base layer. From RHEED observation, it was found that a contamination layer or an amorphous layer formed on the SrSnO/sub 3/ surface after the bilayer was exposed to oxygen plasma for removing a photoresist film. The SrSnO/sub 3/ surface structure was observed to be recovered through the ion etching and subsequent annealing procedure. XRD measurement revealed that FWHM of the SrSnO/sub 3/ [200] rocking curve reduced from that of the as-deposited SrSnO/sub 3/ after an annealing at 715/spl deg/C in 120 mTorr oxygen atmosphere, indicating that crystallinity of the SrSnO/sub 3/ layer was also slightly improved. The recovery process for the SrSnO/sub 3/ layer significantly improved the surface roughness Ra and the J/sub c/ at 4.2 K of the La-YBCO base layer.
Sponsorship	Council on Superconductivity Appl. Superconductivity Conference Inc MIT
Starting Page	157
Ending Page	160
Page Count	4
File Size	522361
File Format	PDF
ISSN	10518223
Volume Number	15
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Nonhomogeneous media Circuits Surface treatment Surface contamination Annealing Crystallization Etching Atmosphere Plasma measurements surface treatment High temperature superconductor La-YBCO multilayer
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Improvement in reproducibility of multilayer and junction process for HTS SFQ circuits

Plasma formation of buffer layers for multilayer resist structures

Preparation of ramp-edge interface modified junctions for HTS SFQ circuits

Optimization of fabrication conditions for multilayer structures with La-doped YBCO groundplane

A novel multilayer process for HTS SFQ circuit

Multilayer HTS SFQ analog-to-digital converters

Cavity-Through Deep Reactive Ion Etching of Directly-Bonded Silicon Wafers

Oxidation of multilayer HTS digital circuits

Improvement of SrTiO/sub 3/ thin film surface polished by chemical mechanical planarization for HTS multilayer device

Fabrication of high-quality multilayer structure for HTS-SFQ circuits using surface treatments

Similar Documents

Improvement in reproducibility of multilayer and junction process for HTS SFQ circuits

Plasma formation of buffer layers for multilayer resist structures

Preparation of ramp-edge interface modified junctions for HTS SFQ circuits

Optimization of fabrication conditions for multilayer structures with La-doped YBCO groundplane

A novel multilayer process for HTS SFQ circuit

Multilayer HTS SFQ analog-to-digital converters

Cavity-Through Deep Reactive Ion Etching of Directly-Bonded Silicon Wafers

Oxidation of multilayer HTS digital circuits

Improvement of SrTiO/sub 3/ thin film surface polished by chemical mechanical planarization for HTS multilayer device

Fabrication of high-quality multilayer structure for HTS-SFQ circuits using surface treatments