NDLI: Improvement in reproducibility of multilayer and junction process for HTS SFQ circuits

Content Provider	IEEE Xplore Digital Library
Author	Wakana, H. Adachi, S. Kamitani, A. Nakayama, K. Ishimaru, Y. Oshikubo, Y. Tarutani, Y. Tanabe, K.
Copyright Year	2002
Abstract	We have developed an HTS multilayer structure including a superconducting ground plane and interface-engineered ramp-edge Josephson junctions for single flux quantum (SFQ) circuits, and tried to improve reproducibility in the multilayer and junction process. We found that one of the crucial factors to improve the reproducibility is use of a ground plane with small average surface roughness (R/sub a/) of typically less than 2 nm and a high T/sub c/ above 87 K. By employing La/sub 0.2/-Y/sub 0.9/Ba/sub 1.9/Cu/sub 3/O/sub x/ (La-YBCO) thin films deposited by dc off-axis magnetron sputtering, such high quality was maintained for 3-month successive use of a ceramic target. Use of such a high-quality ground plane reproducibly led to SrSnO/sub 3//La-YBCO/SrSnO/sub 3//La-YBCO //MgO multilayer structures with R/sub a//spl les/2 nm and 100-junction arrays with 1-/spl sigma/I/sub c/ spread of 6-17% at 4.2 K depending on the average I/sub c/ level. The run-to-run reproducibility of average junction I/sub c/ and sheet inductance of both the base- and counter-electrodes for three samples was /spl plusmn/12%, /spl plusmn/3.0%, and /spl plusmn/3.4%, respectively, which are substantially smaller than those previously reported.
Sponsorship	Council on Superconductivity Appl. Superconductivity Conference Inc MIT
Starting Page	153
Ending Page	156
Page Count	4
File Size	172828
File Format	PDF
ISSN	10518223
Volume Number	15
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reproducibility of results Nonhomogeneous media High temperature superconductors Circuits Josephson junctions Sputtering Rough surfaces Surface roughness Magnetic flux Superconducting magnets SFQ circuit High-temperature superconductor Josephson junction ramp-edge structure
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Influence of Circuit Pattern Layout on Characteristics of Interface-Modified Ramp-Edge Junctions

Logic Operation of HTS SFQ Logic Family

Characterizations of High-Temperature Superconducting Step-Edge Josephson Junction Mixer

Development of Integrated HTS SQUIDs With a Multilayer Structure and Ramp-Edge Josephson Junctions

Characterization of HTS SFQ circuits using interface-engineered Josephson junctions

Non-Destructive Evaluation of Deep-Lying Defects in Multilayer Conductors Using HTS SQUID Gradiometer

A novel multilayer process for HTS SFQ circuit

Fabrication of Ramp-Edge Junctions With High $I_{rm c}R_{rm n}$ Products by Using Cu-Poor Precursor

Multilayer HTS SFQ analog-to-digital converters

Improvement in reproducibility of multilayer and junction process for HTS SFQ circuits

Similar Documents

Influence of Circuit Pattern Layout on Characteristics of Interface-Modified Ramp-Edge Junctions

Logic Operation of HTS SFQ Logic Family

Characterizations of High-Temperature Superconducting Step-Edge Josephson Junction Mixer

Development of Integrated HTS SQUIDs With a Multilayer Structure and Ramp-Edge Josephson Junctions

Characterization of HTS SFQ circuits using interface-engineered Josephson junctions

Non-Destructive Evaluation of Deep-Lying Defects in Multilayer Conductors Using HTS SQUID Gradiometer

A novel multilayer process for HTS SFQ circuit

Fabrication of Ramp-Edge Junctions With High $I_{rm c}R_{rm n}$ Products by Using Cu-Poor Precursor

Multilayer HTS SFQ analog-to-digital converters

Improvement in reproducibility of multilayer and junction process for HTS SFQ circuits