NDLI: Annealing behavior of a doubly MeV implanted silicon

Content Provider	IEEE Xplore Digital Library
Author	Nam-Hoon Cho Tae-Hoon Huh Yoon-Taek Jang Jae-Sang Ro Jae-Geun Oh Kil-Ho Lee Byung-Jin Cho Jong-Choul Kim
Copyright Year	1996
Description	Author affiliation: Dept. of Metall. Eng. & Mater. Sci., Hong Ik Univ., Seoul, South Korea (Nam-Hoon Cho)
Abstract	MeV ion implantation has gained much attention in the field of CMOS retrograde well engineering. Damage formation by high energy implantation has a significant characteristics in that the lattice damage is concentrated near R/sub P/ and isolated from the surface. Si self interstitials are thought to be responsible for the formation of secondary defects upon annealing. The region of excess interstitials could be generated near R/sub P/ by two effects combined with Frenkel separation and dopant activation. However, at the same time, the small amount of vacancy rich zone may exist ahead of an interstitial rich zone. In this study we conducted model experiments to reveal the interactions between different types of defects upon annealing in a doubly MeV implanted silicon using ion species of P and C. The morphology of secondary defects induced by P implantation in a doubly implanted sample was observed to be different from that in singly P implanted one. Meanwhile, no extended defects were observed in the C implanted layer. DCXRD rocking curve analyses for the sample annealed at 550/spl deg/C indicated that a positive strain built up at /spl sim/2.3 /spl mu/m by P implantation was effectively reduced by /spl sim/50% using additional carbon implantation. However, the amount of strain relaxation in the C implanted layer does not decrease upon annealing at 1000/spl deg/C.
Starting Page	661
Ending Page	664
File Size	437161
Page Count	4
File Format	PDF
ISBN	078033289X
DOI	10.1109/IIT.1996.586492
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Annealing Silicon Capacitive sensors Gettering Ion implantation Surface morphology Lattices Semiconductor process modeling Leakage current Impurities
Content Type	Text
Resource Type	Article

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