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Content Provider | IEEE Xplore Digital Library |
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Author | Borland, J.O. Wristers, D. Walker, J. |
Copyright Year | 1996 |
Description | Author affiliation: Ion Technol. Div., Genus Inc., Newburyport, MA, USA (Borland, J.O.) |
Abstract | Using MeV ion implantation and Cz bulk wafer denuding/gettering techniques, we have successfully demonstrated in bulk (non-epi) wafers superior latch-up performance and equivalent surface silicon quality (gate oxide integrity and junction leakage current) to that of p/p+ epi wafers resulting in direct retrofit replacement of epi wafers in manufacturing. Latch-up device characteristics will be presented comparing epi, retrograde wells, buried layers and BILLI (Buried Implanted Layer for Lateral Isolation) structures, Up to a 30/spl times/ reduction in lateral current gain (B/sub 1/) was measured resulting in a 5/spl times/ increase in n+ trigger current at <2.0 um n+ to p+ spacing. Also, optimizing various pre-process and/or process induced denuding and gettering have resulted in epi quality bulk Cz wafer surfaces. For a CMOS Logic manufacturing point of view, up to 16% reduction in total process cycle time/complexity can be realized equating to a cost savings of >$229 per 200 mm wafer. This paper summarizes the various MeV epi replacement alternatives describing the advantages and limitations of each from a production implementation point of view. |
Starting Page | 21 |
Ending Page | 24 |
File Size | 340668 |
Page Count | 4 |
File Format | |
ISBN | 078033289X |
DOI | 10.1109/IIT.1996.586102 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1996-06-16 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Logic devices Gettering Ion implantation Silicon Leakage current Manufacturing Current measurement Gain measurement CMOS process CMOS logic circuits |
Content Type | Text |
Resource Type | Article |
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