NDLI: Assembly technology development for 3D silicon stacked module for handheld products

Content Provider	IEEE Xplore Digital Library
Author	Ganesh, V.P. Lim, S. Witarsa, D. Hnin Wai Yin Kumar, M. Lim, L.A. Yoon, S.W. Kripesh, V.
Copyright Year	2006
Description	Author affiliation: Inst. of Microelectron., Singapore (Ganesh, V.P.; Lim, S.)
Abstract	The objective of this consortium research work is to develop a 3D SiP based on silicon platform technology for integrating heterogeneous multifunctional devices for handheld products with imaging application. The developed 3D SiP can be used for signal speed of 2Gbps with designed silicon through via structures and matched transmission lines. The thermal performance of the 3D SiP is optimized for 3 watts heat dissipation by natural convection cooling. This paper focuses on the process development of five key assembly technologies used to fabricate the 3D silicon carrier SiP. The five key assembly technologies are: (1) wafer thinning, (2) thin flip chip attach on silicon carrier, (3) ultra low loop wire bonding (4), glass cap fabrication and sealing and (5) carrier stacking. The developed SiP has 3 silicon carriers with 4 flip chip and 1 wire bond die chip attached to them and the carrier is stacked one above the other to form the 3D silicon carrier SiP. Key developments in the five assembly technologies include 8" bumped wafer thinning to 100mum, lower flip chip interconnect height between the chip and the carrier down to 35mum, 40 to 50mum low loop wire bonding on overhang by direct reverse wire bonding method using 1 mil diameter Au wire, investigation of 3 types of thin film metallization for wedge bonding, investigation of two different methods in fabricating glass cap 1, Si-anodic bond glass cap 2, SiUV adhesive bond glass cap and investigation on different types of adhesives for cap sealing
File Size	1441918
File Format	PDF
ISBN	1424401526
ISSN	05695503
DOI	10.1109/ECTC.2006.1645822
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Assembly Silicon Wire Wafer bonding Glass Flip chip Signal design Transmission lines Cooling Fabrication
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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