NDLI: Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Content Provider	IEEE Xplore Digital Library
Author	Kacker, K. Sitaraman, S.K.
Copyright Year	1999
Abstract	Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100-mum pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of ~ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society
Starting Page	816
Ending Page	823
Page Count	8
File Size	1251782
File Format	PDF
ISSN	15213331
Volume Number	31
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Costs Dielectric materials Packaging Dielectric substrates Integrated circuit interconnections Wafer scale integration Flip chip Assembly Lead wafer-level packaging (WLP) Chip-to-substrate interconnects compliant interconnects first-level interconnects
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in