NDLI: Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

Content Provider	IEEE Xplore Digital Library
Author	Liao, E.B. Tay, A.A.O. Ang, S.S. Feng, H.H. Nagarajan, R. Kripesh, V.
Copyright Year	1999
Abstract	This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society IEEE Components, Packaging and Manufacturing Technology Society
Starting Page	343
Ending Page	353
Page Count	11
File Size	1265012
File Format	PDF
ISSN	15213323
Volume Number	29
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Numerical analysis Wafer scale integration Integrated circuit interconnections Frequency Packaging Semiconductor device modeling Virtual prototyping Copper Analytical models Geometry wafer-level packaging Compliance electrical parasitic flip-chip multi-copper-column interconnect
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimization of Reliability of Copper Column Flip Chip Packages with Variable Compliance Interconnects

Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance

Super stretched solder interconnects for wafer level packaging

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

Optimization of reliability of wafer level copper column interconnections using a variable compliance interconnect design

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

MicroSMD-a wafer level chip scale package

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Cu interconnects and low-k dielectrics, challenges for chip interconnections and packaging

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

Similar Documents

Optimization of Reliability of Copper Column Flip Chip Packages with Variable Compliance Interconnects

Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance

Super stretched solder interconnects for wafer level packaging

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

Optimization of reliability of wafer level copper column interconnections using a variable compliance interconnect design

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

MicroSMD-a wafer level chip scale package

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Cu interconnects and low-k dielectrics, challenges for chip interconnections and packaging

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging