NDLI: The effect of via size on fine pitch and high density solder bumps for wafer level packaging

Content Provider	IEEE Xplore Digital Library
Author	Chul-Won Ju Seong-Jin Kim Kyu-Ha Pack Hee-Tae Lee Young-Chul Hyun Seong-Su Park
Copyright Year	2002
Description	Author affiliation: Micro-Electron. Technol. Lab., Electron. & Telecommun. Res. Inst., Taejon, South Korea (Chul-Won Ju; Seong-Jin Kim; Kyu-Ha Pack; Hee-Tae Lee; Young-Chul Hyun; Seong-Su Park)
Abstract	This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact aligner with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.
Sponsorship	IEEE Components, Packaging, & Manuf. Technol. Soc. Electronic Components, Assemblies & Mater. Assoc
Starting Page	1178
Ending Page	1181
File Size	404169
Page Count	4
File Format	PDF
ISBN	0780374304
ISSN	05695503
DOI	10.1109/ECTC.2002.1008255
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Copper Resists Chip scale packaging Costs Shape Sputtering Flip chip Electronics packaging Current density
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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