NDLI: Fabrication of compliant, copper-based chip-to-substrate connections

Content Provider	IEEE Xplore Digital Library
Author	Ate He Bakir, M.A. Bidstrup Allen, S.A. Kohl, P.A.
Copyright Year	2006
Description	Author affiliation: Sch. of Chem. & Biomolecular Eng., Georgia Inst. of Technol., Atlanta, GA (Ate He; Bakir, M.A.; Bidstrup Allen, S.A.; Kohl, P.A.)
Abstract	A fabrication process for compliant, copper chip-to-substrate interconnections is described in this paper. Copper interconnect structures were produced through a copper electroplating step filling cavities inside photo-patterned hollow polymer molds. These polymer structures were fabricated on both the chip and the substrate. Copper pillar interconnects are useful as chip-to-substrate power distribution I/O and have been successfully fabricated and assembled. Finite element modeling by ANSYS was used to simulate the mechanics of the copper pillars connection from chip-to-board at elevated temperature conditions. The shear stress distribution was used to analyze the weak points along the pillar. The maximum allowed shear stress was then use to determine the required pillar dimensions (e.g. height and aspect ratio)
File Size	1225778
File Format	PDF
ISBN	1424401526
ISSN	05695503
DOI	10.1109/ECTC.2006.1645622
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Copper Polymers Thermal stresses Current density Resists Chemical technology Assembly Finite element methods Thermal expansion
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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