NDLI: System-on-package (SOP) technology, characterization and applications

Content Provider	IEEE Xplore Digital Library
Author	Knickerbocker, J.U. Andry, P.S. Buchwalter, L.P. Colgan, E.G. Cotte, J. Gan, H. Horton, R.R. Sri-Jayantha, S.M. Magerlein, J.H. Manzer, D. McVicker, G. Patel, C.S. Polastre, R.J. Sprogis, E.S. Tsang, C.K. Webb, B.C. Wright, S.L.
Copyright Year	2006
Description	Author affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY (Knickerbocker, J.U.; Andry, P.S.; Buchwalter, L.P.; Colgan, E.G.; Cotte, J.)
Abstract	A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and burn-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 $W/cm^{2}.$ This IBM research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, characterization, and potential new applications
File Size	736963
File Format	PDF
ISBN	1424401526
ISSN	05695503
DOI	10.1109/ECTC.2006.1645680
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Bandwidth Testing Wiring Microchannel Stacking Packaging Capacitors Cooling Costs
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Characterization of micro-bump C4 interconnects for Si-carrier SOP applications

Development and characterization of low cost ultrathin 3D interconnect

High Density PoP (Package-on-Package) and Package Stacking Development

Low electrical resistance silicon through vias: technology and characterization

Development of 3-dimensional module package, "System Block Module"

Process integration for low-cost system on a package (SOP) substrate

A study on package stacking process for package-on-package (PoP)

Electrical evaluation of flip-chip package alternatives for next generation microprocessors

Reliable through silicon vias for 3D silicon applications

System-on-package (SOP) technology, characterization and applications

Similar Documents

Characterization of micro-bump C4 interconnects for Si-carrier SOP applications

Development and characterization of low cost ultrathin 3D interconnect

High Density PoP (Package-on-Package) and Package Stacking Development

Low electrical resistance silicon through vias: technology and characterization

Development of 3-dimensional module package, "System Block Module"

Process integration for low-cost system on a package (SOP) substrate

A study on package stacking process for package-on-package (PoP)

Electrical evaluation of flip-chip package alternatives for next generation microprocessors

Reliable through silicon vias for 3D silicon applications

System-on-package (SOP) technology, characterization and applications