NDLI: 3D interconnect through aligned wafer level bonding

Content Provider	IEEE Xplore Digital Library
Author	Lindner, P. Dragoi, V. Glinsner, T. Schaefer, C. Islam, R.
Copyright Year	2002
Description	Author affiliation: EV Group, Schaerding, Austria (Lindner, P.; Dragoi, V.; Glinsner, T.; Schaefer, C.)
Abstract	Wafer level packaging and 3D interconnect technologies are driven by increasing device density and functionality as well as reduction of total packaging cost. Key enabling technologies for 3D interconnect are high precision alignment and bonding systems and thick resist processing. A unique processing equipment has been developed to meet high volume production requirements. This paper reviews advances in equipment processing capabilities and provides a guideline for new processing techniques available. Wafer to wafer alignment can be carried out in various ways. Traditionally aligned wafer bonding is a well-established technology in the MEMS industry. Special requirements for 3D interconnects are high accuracy, the use of single side processed wafers and 8 inch capability. A comparison of wafer alignment technologies is presented. Also, a novel face-to-face alignment method is described and analyzed in terms of alignment accuracy before and after bonding. Wafer bonding is carried out subsequent to the alignment step in a separate process module. A summary of different bonding methods is given. Intermediate layers that act as bonding agent can be spun on to the wafer. Such coating processes for wafer level packaging applications vary greatly from the requirements for VLSI processing. VLSI photoresist processes use thin layers to transfer small features with sub-micron tolerances. Wafer level bumping typically is performed with 5-150 /spl mu/m films, to transfer large (20-250 /spl mu/m) features, with tolerances approaching micron scale. HDI applications require thicker adhesive layers. The paper concludes with application examples with different intermediate layers such as BCB.
Sponsorship	IEEE Components, Packaging, & Manuf. Technol. Soc. Electronic Components, Assemblies & Mater. Assoc
Starting Page	1439
Ending Page	1443
File Size	602061
Page Count	5
File Format	PDF
ISBN	0780374304
ISSN	05695503
DOI	10.1109/ECTC.2002.1008295
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer bonding Wafer scale integration Resists Very large scale integration Packaging machines Cost function Production Guidelines Micromechanical devices Coatings
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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