NDLI: Application of no-flow underfill for a reliable high performance Flip Chip Flex BGA

Content Provider	IEEE Xplore Digital Library
Author	Poi-Siong Teo Lim, S.P.-S. Tai-Chong Chai Iyer, M.K.
Copyright Year	2002
Description	Author affiliation: Inst. of Microelectron., Singapore, Singapore (Poi-Siong Teo; Lim, S.P.-S.; Tai-Chong Chai; Iyer, M.K.)
Abstract	A Flip-Chip Flex BGA with commercial reflowable (no-flow) underfill is developed in this work for applications in the domain of 700 I/Os, 5 GHz frequency bandwidth and 20 W power dissipation. An encouraging package reliability performance is achieved mainly through package design, selection of appropriate reflowable underfill and optimization of the flip chip assembly process. We focus on a detailed discussion of the various considerations and methodologies adopted in the underfill selection and assembly optimization process. A reflowable or no-flow underfill was selected for this package after a balanced consideration of its moisture test and thermal cycling reliability potential, processability and cycle time. Details of the considerations and characterization methodology are reported. Through Design of Experiments (DOE), a process window for this underfill was identified. The effects of various key process parameters, such as reflow temperature ramp-up rate, die placement force and substrate preheating temperature, are also discussed.
Sponsorship	IEEE Components, Packaging, & Manuf. Technol. Soc. Electronic Components, Assemblies & Mater. Assoc
Starting Page	425
Ending Page	431
File Size	788309
Page Count	7
File Format	PDF
ISBN	0780374304
ISSN	05695503
DOI	10.1109/ECTC.2002.1008131
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Packaging Assembly Temperature Frequency Bandwidth Power dissipation Design optimization Optimization methods Moisture
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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