NDLI: System on chip design methodology applied to system in package architecture

Content Provider	IEEE Xplore Digital Library
Author	Goetz, M.
Copyright Year	2002
Description	Author affiliation: Alpine Microsystems, Dallas, TX, USA (Goetz, M.)
Abstract	There are two competing technologies pursuing the 'holy grail' of complete system integration. Today, the most common method used to create the 'system' is to mount separately packaged ICs on a next-level substrate. Even with a low pin count, a package is typically several times larger than the IC, to accommodate the low wiring density on the PCB. High-performance systems, such as network processor systems, require high data bandwidth between key components and thus need an increased number of signal I/Os. Wide I/O busses switching at high speeds consequently require a larger number of power and ground pins to reduce switching noise. As a result, system performance is limited by increasing package size and the associated parasitic inductance and capacitance of the package and its connection on the PCB. System on chip (SoC) architecture attempts to integrate many functions, both analog and digital into a monolithic device. The successes are many, but so are the challenges. Many functions cannot be optimized due to the limitation of the semiconductor substrate used. Also, as defect density scales with area, the notion of integrating large scale functions (memory, switch fabrics) with small scale functions (rf devices) results in compounded yield impacts. System in Package (SiP) technology allows heterogeneous devices to be integrated into a small form factor. The integration technology includes embedded devices in the substrate and 3 dimensional chip-stacking approaches. By using a silicon based SiP, a copper/low K interconnect defined by lithographic processes on silicon offers very dense routing with high speed, low noise signal paths. The ICs used in the SiP can be designed to leverage the high density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can dramatically decrease system power requirements and thermal dissipation. The lower bus power can be traded against higher bus frequency to improve performance at a fixed power level.
Sponsorship	IEEE Components, Packaging, & Manuf. Technol. Soc. Electronic Components, Assemblies & Mater. Assoc
Starting Page	254
Ending Page	258
File Size	716221
Page Count	5
File Format	PDF
ISBN	0780374304
ISSN	05695503
DOI	10.1109/ECTC.2002.1008103
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Design methodology Substrates Bandwidth Signal processing Semiconductor device noise Semiconductor device packaging Switches Silicon Integrated circuit packaging
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Multi-flip chip on lead frame overmolded IC package: a novel packaging design to achieve high performance and cost effective module package

Chip-package co-design for high performance and reliability off-chip communications

Plastic chip carrier package

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

Mixed signal system design: a system integration and packaging course developed for chip and system designers

Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance

The BCML Circuit and Packaging System

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

Thermal analysis of a chip scale package technology

System on chip design methodology applied to system in package architecture

Similar Documents

Multi-flip chip on lead frame overmolded IC package: a novel packaging design to achieve high performance and cost effective module package

Chip-package co-design for high performance and reliability off-chip communications

Plastic chip carrier package

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

Mixed signal system design: a system integration and packaging course developed for chip and system designers

Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance

The BCML Circuit and Packaging System

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

Thermal analysis of a chip scale package technology

System on chip design methodology applied to system in package architecture