NDLI: Three-dimensional very thin stacked packaging technology for SiP

Content Provider	IEEE Xplore Digital Library
Author	Yano, Y. Sugiyama, T. Ishihara, S. Fukui, Y. Juso, H. Miyata, K. Sota, Y. Fujita, K.
Copyright Year	2002
Description	Author affiliation: Dept. Packaging Dev., Sharp Corp., Tenri, Japan (Yano, Y.; Sugiyama, T.; Ishihara, S.; Fukui, Y.; Juso, H.; Miyata, K.; Sota, Y.; Fujita, K.)
Abstract	In order to achieve the greater compactness, lightness, high- and multi-functionality required of mobile equipment and other electronic devices, we have developed 3D packaging technology which enables free stacking, at the package level, of ultra-thin CSP (which contain 2 or 1 LSI chip(s)). By stacking at the package level, there are no yield problems, and it is easy to perform independent electrical testing, so it is possible to achieve multi-level stacking while freely combining different kinds of LSI chips like memory or ASIC. By making chips and resin molding thinner, lowering wire loops and optimizing the package structure, we achieved higher package density: a single unit (2 chips) package height of 0.55 mmMax., 2 layers (4 chips) with a unit package height of 1.0 mmMax., and 3 layers (6 chips) with a unit package height of 1.5 mmMax. This technology makes it possible to offer ultra-compact systems-in-package (logic + memory) and high-capacity composite memories.
Sponsorship	IEEE Components, Packaging, & Manuf. Technol. Soc. Electronic Components, Assemblies & Mater. Assoc
Starting Page	1329
Ending Page	1334
File Size	803689
Page Count	6
File Format	PDF
ISBN	0780374304
ISSN	05695503
DOI	10.1109/ECTC.2002.1008278
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Packaging machines Stacking Large scale integration Chip scale packaging Performance evaluation Testing Application specific integrated circuits Resins Wire
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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