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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jinbum Kim Noquil, J.A. Teik keng Tan Chung-Lin Wu Seung-Yong Choi |
| Copyright Year | 2005 |
| Description | Author affiliation: Package Knowledge Center, Fairchild Semicond. Corp., Gyunggi-do, South Korea (Jinbum Kim; Noquil, J.A.; Teik keng Tan; Chung-Lin Wu; Seung-Yong Choi) |
| Abstract | Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of different levels of voltage and current on a common silicon substrate with controller IC operating in the range of several volts and milliamps, while power MosFETs at over hundreds of volts and more dozens of amps can also pose as an issue. Nevertheless, module packages having controller IC and power MosFET co-packaged are new. Fairchild semiconductor's advancement in packaging has eliminated these drawbacks with the introduction of multi-flip chip on lead frame over-molded IC package. This new package has a novel packaging concept that uses multi-flip chip technology on the power devices combined with controller IC employing wire bonding technique on one copper lead frame based substrate. The gate and source in power MosFETs are bumped and attached to the copper lead frame by flip chip bonding technology and are routed out of package by solder balls while the drain exposed at the bottom of the package is soldered directly to the board. This is a BGA package with exposed die back for drain. The paper describes the construction of multi-flip chip on lead frame over molded package in Fairchild Semiconductor, its cost effective package designs and manufacturing challenges. |
| Starting Page | 1819 |
| Ending Page | 1821 |
| File Size | 442904 |
| Page Count | 3 |
| File Format | |
| ISBN | 0780389077 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2005.1442043 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-05-31 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit packaging Costs Semiconductor device packaging Substrates MOSFETs Silicon Lead compounds Bonding Copper System-on-a-chip |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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