NDLI: An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

Content Provider	IEEE Xplore Digital Library
Author	Shen-Fu Hsiao Ming-Yu Tsai Ming-Chih Chen Chia-Sheng Wen
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan (Shen-Fu Hsiao; Ming-Yu Tsai; Ming-Chih Chen; Chia-Sheng Wen)
Abstract	An efficient logic synthesis based on pass-transistor logic (PTL) is developed. Instead of using a static CMOS cell library, which usually contains hundreds of different cells, the PTL synthesizer uses only two types of cells: 2-to-1 multiplexers (MUX) and inverters. The PTL synthesizer first employs the Synopsys design compiler (DC) to perform logic translation and minimization for the input HDL descriptions. Then, the PTL-based technology mapping performs area optimization and driving strength selection considering the user's area and/or speed requirements. Experiments show that our synthesizer generates results with better area and/or speed performance compared to previous approaches with CMOS or other PTL cell libraries.
Starting Page	2433
Ending Page	2436
File Size	344599
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465117
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Synthesizers Multiplexing CMOS logic circuits Circuit synthesis Libraries Logic design CMOS technology Pulse inverters Binary decision diagrams Minimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

High-performance multiplexer-based logic synthesis using pass-transistor logic

An efficient algorithm for low power pass transistor logic synthesis

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

On the generation of multiplexer circuits for pass transistor logic

Transistor level synthesis for static CMOS combinational circuits

BDD decomposition for mixed CMOS/PTL logic circuit synthesis

Pass transistor logic ALU design

Buffer minimization in pass transistor logic

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

Similar Documents

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

High-performance multiplexer-based logic synthesis using pass-transistor logic

An efficient algorithm for low power pass transistor logic synthesis

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

On the generation of multiplexer circuits for pass transistor logic

Transistor level synthesis for static CMOS combinational circuits

BDD decomposition for mixed CMOS/PTL logic circuit synthesis

Pass transistor logic ALU design

Buffer minimization in pass transistor logic

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only