NDLI: Energy-saving design technique achieved by latched pass-transistor adiabatic logic

Content Provider	IEEE Xplore Digital Library
Author	Junyoung Park Sung Je Hong Jong Kim
Copyright Year	2005
Description	Author affiliation: Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea (Junyoung Park; Sung Je Hong; Jong Kim)
Abstract	In recent years, low power circuit design has been an important issue in system on chip (SoC) and VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. It is expected that adiabatic logic will be a substitute for static CMOS logic especially for the purpose of low power applications. Despite the proposal of several adiabatic logic families, no research has been done on the technique for replacing CMOS circuits with adiabatic logic. In this paper, we propose a latched pass-transistor adiabatic logic (LPAL) and an energy-saving design scheme for low power applications. LPAL replaces CMOS circuits, providing more energy-efficiency than other forms of adiabatic logic. In simulation, we compared the energy consumption of pass-transistor adiabatic logic (PAL), a good model for conventional adiabatic logics, with that of LPAL. Simulation results show that the LPAL circuit results in power savings of 44% over PAL.
Starting Page	4693
Ending Page	4696
File Size	254196
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465680
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic design CMOS logic circuits Circuit synthesis Circuit simulation System-on-a-chip Very large scale integration Proposals CMOS technology Energy efficiency Energy consumption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in