NDLI: An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications

Content Provider	IEEE Xplore Digital Library
Author	Ting Wu Hanumolu, P.K. Un-Ku Moon Mayaram, K.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA (Ting Wu; Hanumolu, P.K.; Un-Ku Moon; Mayaram, K.)
Abstract	We present a new dual-loop frequency synthesizer for 5 GHz wireless local-area network (WLAN) applications. In line with the IEEE 802.11a standard, the output frequency is targeted at 5.15 GHz to 5.35 GHz, with a frequency step of 5 MHz. To make the use of the ring-type VCO feasible for this application, we adopted a dual-loop frequency synthesizer architecture similar to that of T. Aytur and J. Khoury (see IEEE Int. Symp. Circuits and Systems, p.17-20, 1997). However, it is critical that the primary loop of such a dual-loop frequency synthesizer is supported by a low-noise reference (by the peripheral loop). To address this problem, we propose a new fractional frequency multiplying delay-locked loop (FMDLL) working as the peripheral loop. MATLAB simulation results demonstrate the phase noise improvement by the use of the proposed FMDLL compared to the conventional design.
Starting Page	3986
Ending Page	3989
File Size	233410
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465504
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Wireless LAN Local area networks Voltage-controlled oscillators Circuits and systems Frequency locked loops Delay MATLAB Circuit simulation Phase noise
Content Type	Text
Resource Type	Article

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