NDLI: An efficient algorithm for low power pass transistor logic synthesis

Content Provider	IEEE Xplore Digital Library
Author	Shelar, R.S. Sapatnekar, S.S.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Shelar, R.S.)
Abstract	In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power reduction in PTL circuits to that of BDD decomposition and solve the latter using the max-flow min-cut technique. We use transistor level power estimates to guide the BDD decomposition algorithm. We present the results obtained by running our algorithm on a set of MCNC benchmark circuits, and show on an average of 47% power reduction over these circuits; the comparison with the previously proposed low power pass transistor logic synthesis algorithms shows an average improvement of over 23% over the best previously published approach.
Sponsorship	VLSI Soc. India (VSI)
Starting Page	87
Ending Page	92
File Size	372251
Page Count	6
File Format	PDF
ISBN	0769514413
DOI	10.1109/ASPDAC.2002.994890
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Binary decision diagrams Power dissipation Clocks Logic circuits Codecs CMOS logic circuits Switching circuits Inverters Circuit synthesis Combinational circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

Super low power 8-bit CPU with pass-transistor logic

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

Transistor level synthesis for static CMOS combinational circuits

A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

Low power adiabatic multiplier with complementary pass-transistor logic

Multi-level pass-transistor logic for low-power ULSIs

Optimization of combinational and sequential logic circuits for low power using precomputation

A complete model for glitch analysis in logic circuits

An efficient algorithm for low power pass transistor logic synthesis

Similar Documents

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

Super low power 8-bit CPU with pass-transistor logic

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

Transistor level synthesis for static CMOS combinational circuits

A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

Low power adiabatic multiplier with complementary pass-transistor logic

Multi-level pass-transistor logic for low-power ULSIs

Optimization of combinational and sequential logic circuits for low power using precomputation

A complete model for glitch analysis in logic circuits

An efficient algorithm for low power pass transistor logic synthesis