NDLI: A multiplication-accumulation computation unit with optimized compressors and minimized switching activities

Content Provider	IEEE Xplore Digital Library
Author	Li-Hsun Chen Chen, O.T.-C. Teng-Yi Wang Yung-Cheng Ma
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan (Li-Hsun Chen; Chen, O.T.-C.)
Abstract	A low-power multiplication-accumulation computation (MAC) unit using the radix-4 Booth algorithm is proposed; its architectural complexity is reduced and switching activities are minimized. However, to maintain a high performance, the critical delays and hardware complexities of MAC units are explored to derive a MAC unit with high performance and low hardware complexity. A carry-save addition operation with optimized compressors is proposed to omit the use of half adders to reduce the hardware complexity further. A scheme to reduce switching activity is also proposed to lower the power consumption of the MAC unit. In performing a MAC for X/spl times/Y+Z, the effective dynamic ranges of X and Y are detected; the one with the smaller effective dynamic range is processed for Booth decoding so as to increase the probability of the partial products being zero, and thus the switching activity is reduced. Also, the effective dynamic range of the result from this multiplication is estimated and compared with the effective dynamic range of the datum, Z. The larger effective dynamic range of the two data is considered as the effective word length for an addition operation. Pipelined latches are used to make the noneffective operation maintain the status of the previous operation so as to reduce the switching activities from the addition performed in MAC. After the addition operation, sign extension is performed on the result from the effective sign bit copied to non-effective bits to derive at a correct output datum. Compared to conventional MAC units, the proposed one is able to reduce 21.09% to 43.74% of power consumption. Additionally, the proposed MAC unit outperforms conventional ones in comparing the product of critical delay, area, and power consumption.
Starting Page	6118
Ending Page	6121
File Size	456644
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1466036
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Compressors Energy consumption Hardware Computer architecture Delay Dynamic range Switching circuits Communication switching Digital signal processing Switched capacitor circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Systolic parasitic insensitive switched capacitor and digital filters

Companding switched capacitor filters

Digital Multiplication using Continuous Valued Digits

A new switched capacitor circuit for parallel-pixel image processing [vision sensor integrated signal processing]

High frequency switched capacitor FIR filters using parallel cyclic type circuits

Continuous and switched-capacitor multiphase oscillators

A low-power digital signal processor core by minimizing inter-data switching activities

A new pipelined array architecture for signed multiplication

Data wordlength reduction for low-power signal processing software

A multiplication-accumulation computation unit with optimized compressors and minimized switching activities

Similar Documents

Systolic parasitic insensitive switched capacitor and digital filters

Companding switched capacitor filters

Digital Multiplication using Continuous Valued Digits

A new switched capacitor circuit for parallel-pixel image processing [vision sensor integrated signal processing]

High frequency switched capacitor FIR filters using parallel cyclic type circuits

Continuous and switched-capacitor multiphase oscillators

A low-power digital signal processor core by minimizing inter-data switching activities

A new pipelined array architecture for signed multiplication

Data wordlength reduction for low-power signal processing software

A multiplication-accumulation computation unit with optimized compressors and minimized switching activities