NDLI: An efficient pre-traceback approach for Viterbi decoding in wireless communication

Content Provider	IEEE Xplore Digital Library
Author	Yao Gang Arslan, T. Erdogan, A.T.
Copyright Year	2005
Description	Author affiliation: Sch. of Electr. Eng., Edinburgh Univ., UK (Yao Gang; Arslan, T.; Erdogan, A.T.)
Abstract	An efficient pre-traceback architecture is proposed for the survivor path memory unit (SMU) of a Viterbi decoder (VD) targeting wireless communication applications. Compared to the conventional traceback approach, which is based on three kinds of memory access operations (decision bits write, traceback read and decode read), the proposed architecture exploits the inherent parallelism between the decision bit write and the decode traceback operation by introducing a pre-traceback operation. The proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback approach achieves up to 11% energy efficiency and 21% area saving compared to the conventional traceback architecture for typical wireless applications.
Starting Page	5441
Ending Page	5444
File Size	130495
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465867
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Viterbi algorithm Wireless communication Maximum likelihood decoding Registers Recursive estimation State estimation Read-write memory Delay Energy efficiency Error correction
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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