NDLI: A novel reseeding mechanism for pseudo-random testing of VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Jiann-Chyi Rau Ying-Fu Ho Po-Han Wu
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan (Jiann-Chyi Rau; Ying-Fu Ho; Po-Han Wu)
Abstract	During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random, and use an additional bit counter to improve test length and achieve high fault coverage. The fact is that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change them to useful patterns, and when the patterns change, we pick out the numbers with less bits, leading to very short test length. The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% fault coverage can be achieve.
Starting Page	2979
Ending Page	2982
File Size	181872
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465253
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Very large scale integration Circuit faults Built-in self-test Counting circuits Logic testing Electrical fault detection Test pattern generators Fault detection Automatic testing
Content Type	Text
Resource Type	Article

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