NDLI: A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate

Content Provider	IEEE Xplore Digital Library
Author	Payton, M.W. Fat Duen Ho
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA (Payton, M.W.; Fat Duen Ho)
Abstract	The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR gate and NAND gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR gate and the NAND gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears between two devices connected in series. The results compared well with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz.
Starting Page	5657
Ending Page	5661
File Size	179249
Page Count	5
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Semiconductor device modeling Physics computing Circuit simulation SPICE Computational modeling CMOS logic circuits Voltage Geometry Transient response
Content Type	Text
Resource Type	Article

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