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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Stine, J.E. Schulte, M.J. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA (Stine, J.E.) |
| Abstract | This paper presents the design of a combined two's complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both operand types into one unit, while still maintaining low area and high speed. The comparator design uses a novel magnitude comparator with logarithmic delay, plus additional logic to handle both two's complement and floating point operands. The comparator fully supports 32-bit and 64-bit floating-point comparisons, as defined in the IEEE 754 standard, as well as 32-bit and 64-bit two's complement comparisons. Area and delay estimates are presented for designs implemented in AMI C5N 0.5 /spl mu/m CMOS technology. |
| Starting Page | 89 |
| Ending Page | 92 |
| File Size | 156307 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780388348 |
| DOI | 10.1109/ISCAS.2005.1464531 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-05-23 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay estimation CMOS technology Design engineering Ambient intelligence Very large scale integration Algorithm design and analysis FCC Paper technology Maintenance engineering Added delay |
| Content Type | Text |
| Resource Type | Article |
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